Overview

Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!
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indie is empowering the Autotech revolution with next generation automotive semiconductors and software platforms. We focus on edge sensors spanning multiple modalities including LiDAR, radar, ultrasound and vision for Advanced Driver Assistance Systems (ADAS), autonomous vehicles, connected car, user experience and electrification applications.

Responsibilities

• In depth knowledge of Semiconductor Manufacturing Process
• Previous team mentorship and management experience
• Experience recruiting, training, and retaining test engineering staff
• Deep understanding of Digital, RF and Analog Fundamental, Design for Test and Manufacturing Concepts
• Exposures to post-Silicon validation, silicon bring-up, testing/debug/root cause of circuit marginalities, product engineering, foundry manufacturing, etc.
• Experience working on Digital, Mixed Signal, PMIC Devices with hands on VLSI ATE experience.
• Experience leading team of junior/mid-level/senior engineers
• Experience working with cross-functional teams
• System level & RF/SOC experience is a plus
• Strong programming skills for writing and debugging test programs and HW related issues.
• Competency in programming with Scripting languages (ie., Perl/Python) and high-level languages (ie., C/C++ or JAVA)
• Preferred knowledge on V93000 SOC Tester – Smartest 7 or Smartest 8
• Validated experience with test equipment (ie., oscilloscope, logic analyzer, etc)
• Understanding test execution through both functional mode and DFX hooks
• You are comfortable working primarily in a lab environment
• You have good experimental technique, techniques of problem localization and root-cause
• You have system level understanding of CPU/SoC architecture, Memories (DDR, NAND), Systems
• Good data analysis skills and attention to details

Nice-to-haves (in at least one and preferably several areas):

• Chip design background in circuit/physical design (timing closure, power, etc.) or DV (correlating SW signatures to block level tests).
• Post silicon physical debug background in speed-path/Vmin, memory arrays, clocking or yield improvements.
• Post silicon logic debug background in exercising various DFX features, analyzing scan-dump/mem-dump, suggesting tests in both system level or in DV
• Deep understanding of boot process, boot-loaders, embedded software, micro-kernel and able to tweak system tests.
• Product engineering background and familiarity with ATE coverage, margin, binning, scan pattern generation, etc.
• Good IP knowledge in some PHY blocks (eg. DDR, PCIe, USB, etc)

Requirements

• Lead the Test Engineering team, including allocation of resources and work, leading indie’s test strategy, mentoring and training junior engineers, recruitment, and managing performance.
• Understanding new chip features and define coverage applicable to our test environment
• Executing a validation test on large volume and analyze results (pass/failure/artifacts/surprises/etc.)
• Be the first line of defense when failure occurs to isolate (setup, code, artifacts, silicon issues, logic/physical, identify blocks, etc.).
• Once isolated, working with domain experts to define debugs and come up with a root cause.
• Assisting in driving a fix. Maintain and create automation scripts/flows for self-consumption as well as others.
• Able to summarize debugs/findings and think along the line of improvements in both DFX features and test coverage.