KTM50x0

Part Number	Functional Description	Marking	Operating Temperature	Package	External Package
KTM5000B0	DP- 4 lanes No DSC	KTM5000B0	0°C to +70°C	289-LFBGA	TRAYS
KTM5000B0T	DP- 4 lanes No DSC	KTM5000B0	0°C to +70°C	289-LFBGA	Tape & Reel
KTM5010B0	DP 4 Lanes DSC	KTM5010B0	0°C to +70°C	289-LFBGA	TRAYS
KTM5010B0T	DP 4 Lanes DSC	KTM5010B0	0°C to +70°C	289-LFBGA	Tape & Reel
KTM5020B0	USB-C/ DP alt-mode DP 4 lanes OR 2 lanes DP and 2 lanes USB3.2. No DSC	KTM5020B0	0°C to +70°C	289-LFBGA	TRAYS
KTM5020B0T	USB-C/ DP alt-mode DP 4 lanes OR 2 lanes DP and 2 lanes USB3.2. No DSC	KTM5020B0	0°C to +70°C	289-LFBGA	Tape & Reel
KTM5030B0	USB-C/ DP alt-mode DP 4 lanes OR 2 lanes DP and 2 lanes USB3.2. DSC	KTM5030B0	0°C to +70°C	289-LFBGA	TRAYS
KTM5030B0T	USB-C/ DP alt-mode DP 4 lanes OR 2 lanes DP and 2 lanes USB3.2. DSC	KTM5030B0	0°C to +70°C	289-LFBGA	Tape & Reel

The KTM50x0 is an advanced DisplayPort1.4a MST hub with an integrated USB type-C de-multiplexer, targeted primarily for Mobile Notebook accessory and display applications. This device functions as a multi-stream audio-video splitter and protocol converter with an HDCP1.x/ HDCP2.3 repeater supporting both compressed (DSC) and uncompressed AV streams.

KTM50x0 has a DP alt-mode capable USB Type-C Upstream Facing Port (UFP). The four high speed lanes of UFP can receive DP1.4a MST audio-video and USB3.2 Gen2 data streams simultaneously. The input lane mapping is flexible and meets standard DP or the USB Type-C connector with flip orientation requirements. The incoming DP and USB signals are de-multiplexed, retimed, and transmitted on the Downstream Facing Ports (DFP). The KTM50x0 consists of three AC coupled DP/DP++ or DC coupled HDMI/DVI DFPs, each with four high-speed lanes and one USB port with USB3.2 TX and RX pair. The Stream Routing Logic in KTM50x0 allows flexible routing of incoming DP MST stream converted into any combination of MST or SST streams on any of the DFP video ports with link rate and lane count change option. Also, the SST stream can be replicated on two or more DFP ports. In addition, the DP SST stream can be converted into a HDMI or DVI output (TMDS signal format).

The combo receiver in KTM50x0 supports all DP standard data rates up to HBR3 (8.1 Gbps/lane) and USB3.2 Gen1 (5.0 Gbps) and Gen2 (10.0 Gbps). The
dual mode (DP++) transmitters support DP standard data rates up to 8.1 Gbps/lane and TMDS data rates up to 6.0 Gbps/lane. The side-band channel uses 1.0 Mbps Manchester-coded AUX signaling for DP and DDC signaling up to 100kbps for the HDMI interface.

KTM50x0 is capable of processing up to six DP audio- video streams compressed or uncompressed. FEC decoding and encoding is employed for the reliable reception and transmission of DSC1.2a compressed streams. These streams can be part of one single large video timing or six independent video timings from a single source with corresponding independent multi-channel audio. The highest video timing per stream and the number of streams transported is limited by the DP1.4a and HDMI2.0 link bandwidth. When the received DP MST stream is in DSC1.2a compressed format, KTM50x0 can decode the streams (max two streams) or pass through to the downstream sink or to another cascaded KTM50x0 device. If a DP source sends an 8k4k60Hz RGB/ YCC444 DSC1.2a encoded video as four 4k2k60Hz MST, then two KTM50x0 devices are needed to decode all four streams. KTM50x0 supports both RGB 444 and YCC444/422/420 video pixel encoding formats with a color depth up to 16 bpc (bits per component or 48 bits per pixel). It has a pixel processing unit capable of video pixel encoding format conversion from RGB444 to YCC444 with bit depth expansion and down scaling from YCC444 to YCC422/420. Pixel format conversion along with horizontal blanking expansion improves interoperability and smooth rendering of CVT video timings from a mobile PC on a consumer displays such as TVs and projectors which supports only CEA timings.

KTM50x0 processes High Dynamic Range (HDR) video content specified in BT601, BT709, BT2020, BT2100 , Adobe RGB colorimetry format with the proper metadata conversion from DP to HDMI. It also offers secure reception and transmission of high bandwidth digital audio and video content with HDCP1.x or HDCP2.3 content protection. As a branch device KTM50x0 functions as a HDCP1.x and HDCP2.3 repeater between the DP source and DP or HDMI sink.

KTM50x0 uses an external 25 MHz reference clock for its operation. The reference clock can be generated from a 25MHz crystal or from an external source.

It has a 300MHz ARM Cortex M3 CPU with on-chip memories for code and data storage. The peripheral subsystem includes SPI, UART (debug only), and I2C master, slave interfaces. An internal Power-On Reset (POR) circuit senses the voltage on the reset input and provides the chip reset during system powerup. The KTM50x0 uses an external 16 Mbit SPI flash memory for storing the RSA-2048 signed application firmware with fail-safe recovery. At boot up, the CPU goes through a secure boot process authenticating the application code image stored in the SPI flash.

It supports both standard mode and quad mode SPI operation. Firmware update for the SPI flash is done securely through the DP AUX_CH or I2C host interface (Secure In-System-Programming).